In computer networks, a number of network stations are typically interconnected via a communications medium. For example, Ethernet 802.3 is a commonly used local area network (LAN) scheme in which multiple stations are connected to a shared serial data path. These stations often communicate with a switch located between the data path and the stations connected to that path. The switch typically controls the communication of data and includes logic for receiving and forwarding data frames to their appropriate destinations.
When all of the stations connected to the network are simultaneously operating, data traffic on the shared serial path can be heavy with little time between data frames. Accordingly, some switches transfer the data frames to an external memory for storage to reduce on-chip memory requirements. The data frames must then be transferred back to the switch before transmitting the frames to their respective destinations. With increased network throughput requirements, such a processing arrangement often results in an unacceptable delay in forwarding the data frames.
One conventional way of reducing the time for processing data frames is to increase the width of the external memory bus. For example, as the number of ports supported by the switch increases, the data width of the external memory bus typically increases so that the data transfer rate is able to keep up with both the inbound and outbound packet rates.
As the width of the external memory bus increases, however, the bus efficiency decreases due to transfers involving the last few bytes of a data frame. For example, assume that the external memory bus is 16 bytes wide and the switch receives a data frame 65 bytes in length. In this case, five separate transfers are required to store all of the data to the external memory. On the last transfer, however, only one byte of meaningful data is transferred with the other 15 bytes being wasted. Accordingly, the bus efficiency for such a frame is 65/(5×16) or 81.25%. If all the ports receive similar packets, the switch resources will be used up transferring meaningless data and the data throughput of the switch will be significantly reduced.
Another drawback with increasing the width of the external memory bus involves memory management overhead. Each data frame stored to external memory typically includes a buffer header used for memory management. The buffer header may include information such as the address of the next buffer storing a portion of the data frame, the last buffer bit, etc. This buffer header information is usually a few bytes in length. When updating the buffer header or when accessing the header information for retrieving the stored data frame, only the few header bytes are transferred over the external memory bus with the remaining bytes being zero filled or filled with other meaningless data. This further decreases the bus efficiency and wastes valuable bandwidth.